Hi, I'm working on a Xilinx FPGA based project where we just upgraded the ram to Crucial's CT12864AC667. Unknown at the time of purchase the system wasn't as Plug-And-Play as we thought. Instead we need to create a memory controller with the specific latencies for the ram in use. Does crucial offer publicly any further documentation on values such as: tRP - Minimum PRECHARGE command period tWR - Minimum write recover time. (there's quite a few more) Thank you, Rob.
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